1. Technical Field
The present invention is related generally to complementary metal-oxide-semiconductor (CMOS) field-effect transistors, and more particularly to CMOS with embedded source/drain stressors and CMOS with raised source/drain.
2. Discussion of Related Art
Complementary metal-oxide semiconductor (CMOS) field-effect transistors (FETs) are employed in almost every electronic circuit application, such as signal processing, computing, and wireless communications. CMOS chips in manufacturing comprise of planar thick-body devices on bulk Si substrates or on silicon-on-insulator (SOI) substrates. Thick-body FETs on SOI substrates are also referred to as partially-depleted SOI (PDSOI) FETs. A CMOS chip consists n-channel FETs (NFETs), p-channel PFETs (PFETs), and other electronic devices, such as but not limited to, diodes, resistors, capacitors, and inductors.
In CMOS circuits/chips comprising of either bulk Si or PDSOI FETs, embedded SiGe (eSiGe) source/drain (SD) is used in PFETs for obtaining uniaxial compressive stress in the channel for mobility and performance enhancement. The eSiGe SD is typically fabricated by (i) forming nitride disposable sidewall spacers and nitride gate cap to encapsulate the PFET gates, and forming nitride disposable cover on the NFET gates, (ii) etching a recess in the PFET SD regions using reactive-ion etch (RIE), and (iii) epitaxially growing SiGe in the recessed PFET SD regions, selective to nitride and oxide. Therefore, the eSiGe SD is laterally a distance dPFET away from the gate edge. Since the gate defines the channel region underneath it, the eSiGe SD stressor is, therefore, a distance dPFET away from the channel.
Embedded SiC source/drain (SD) leads to mobility and performance enhancement when used in NFETs for obtaining uniaxial tensile stress in the channel. The eSiC SD is typically fabricated using processes similar to eSiGe SD fabrication. That is, eSiC SD is fabricated by (i) forming nitride disposable sidewall spacers and nitride gate cap to encapsulate the NFET gates, and forming nitride disposable cover on the PFET gates, (ii) etching a recess in the NFET SD regions using reactive-ion etch (RIE), and (iii) epitaxially growing SiC in the recessed NFET SD regions, selective to nitride and oxide. Therefore, similar to the eSiGe case, the eSiC SD stressor is a distance dNFET away from the channel.
The effectiveness of eSiC and eSiGe SD stressors in enhancing carrier mobility and FET performance depends on the proximity (that is, the distance dNFET or dPFET) of the stressors to the channel. A closer proximity, that is, smaller dNFET or dPFET, leads to improved stress coupling to the channel, thereby leading to higher enhancement of carrier mobility and FET performance.
Conventional methods of fabrication, similar to the one noted above, can be used for fabricating CMOS structures with NFETs having eSiC SD and PFETs having eSiGe SD. One can also reverse the sequence of eSiGe and eSiC SD formation with eSiC SD for NFETs being formed prior to eSiGe SD for PFETs. Conventional methods of fabrication lead to CMOS structures where the proximity of the NFET and PFET embedded SD stressors to the respective channels is different. The embedded SD that is formed second is further away from its channel than the one that is formed first. Therefore, in these CMOS structures, the effectiveness of the embedded SD stressors will be more for the embedded SD that is formed first and will be less for the embedded SD that is formed next.
Scaling down the gate length of both NFETs and PFETs in CMOS circuits to shorter dimensions leads to increased CMOS circuit speed. The entire semiconductor industry has followed this since the advent of CMOS. However, detrimental short-channel effects lead to high off-state leakage currents in CMOS devices with short gate lengths, thereby increasing the power consumption. In case of extreme short-channel effects, CMOS circuits fail to operate.
Narrow-body planar and non-planar FETs, such as, extremely-thin SOI (ETSOI) FETs, FinFETs, and trigates exhibit significantly superior short-channel characteristics compared to thick-body bulk Si and PDSOI FETs. These FET architectures are, therefore, attractive candidates for future-generation CMOS technology. Narrow-body FETs suffer from high series resistance. This problem is alleviated by epitaxially forming raised source/drain (RSD). This structure can be formed using process similar to those used for forming embedded SD (with the general exception of skipping the recess etch step). Similarly, one can form CMOS using thin-body FETs with SiC RSD for NFETs and SiGe RSD for PFETs.
Similar to the case of thick-body CMOS with embedded SD discussed earlier, eSiC and eSiGe RSD can also impart favorable tensile and compressive stress to NFET and PFET channels, respectively. Also, similar to the thick-body CMOS case, it is also well known in literature that the effectiveness of eSiC and eSiGe RSD stressors in enhancing carrier mobility and FET performance depends on the proximity (that is, the distance dNFET or dPFET) of the stressors to the channel. A closer proximity, that is, smaller dNFET or dPFET, leads to better stress coupling to the channel, thereby leading to higher enhancement of carrier mobility and FET performance.
Therefore, a need exists for a method for the fabrication of embedded SD CMOS where the proximity of an embedded SD is substantially the same for both NFETs and PFETs and for fabrication of thin-body FET CMOS with SiC RSD NFETs and SiGe RSD PFETs with the proximity of the RSD being low and substantially the same for both NFETs and PFETs.